Error Detection of Data Conversion in Flash ADC using Code Width Based Technique
نویسندگان
چکیده
منابع مشابه
metrics for the detection of changed buildings in 3d old vector maps using als data (case study: isfahan city)
هدف از این تحقیق، ارزیابی و بهبود متریک های موجود جهت تایید صحت نقشه های قدیمی سه بعدی برداری با استفاده از ابر نقطه حاصل از لیزر اسکن جدید شهر اصفهان می باشد . بنابراین ابر نقطه حاصل از لیزر اسکنر با چگالی حدودا سه نقطه در هر متر مربع جهت شناسایی عوارض تغییر کرده در نقشه های قدیمی سه بعدی استفاده شده است. تمرکز ما در این تحقیق بر روی ساختمان به عنوان یکی از اصلی ترین عارضه های شهری می باشد. من...
Analysis of Flash ADC Data With VERITAS
VERITAS employs a 12m segmented mirror and pixellated photomultiplier tube camera to detect the brief pulse of Cherenkov radiation produced by the extensive air shower initiated by a cosmic high-energy gamma ray. The VERITAS data acquisition system consists of a 500 Mega-Sample-PerSecond custom-built flash ADC system, which samples the Cherenkov light pulse every 2 nanoseconds. The integrated c...
متن کاملA Fault Diagnosis Technique for Flash ADC ’ s
This paper addresses the problem of diagnosis of flash ADC’s and proposes a fault diagnosis technique which employs the Differential NonLinearity (DNL) test data for fault location and identification of the analog components in the converter. In the flash ADC, a fault causes deviation of DNL data from the ideal one. Hence, DNL data can be considered as a functional signature of the ADC. This pr...
متن کاملReducing the Power Consumption in Flash ADC Using 65nm CMOS Technology
Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreas...
متن کاملReducing the Consumption Power in Flash ADC Using 65nm CMOS Technology
This paper presents a new method to reduce consumption power in flash ADC in 65nm CMOS technology. This method indicates a considerable reduction in consumption power, by removing comparators memories. The simulations used a frequency of 1 GHZ, resulting in decreased consumption power by approximately 90% for different processing corners. In addition, in this paper the proposed method was desig...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Procedia Computer Science
سال: 2019
ISSN: 1877-0509
DOI: 10.1016/j.procs.2020.01.078